A monolithic silicon integrated circuit ("IC") contains a group of transistors and other basic semiconductor devices formed out of a monosilicon semiconductor die having a generally flat principal surface referred to here as the upper monosilicon surface. An electrical interconnection system situated on the upper MS surface appropriately interconnects the transistors and other basic devices. The semiconductor electrodes of each transistor conventionally extend to the upper MS surface where they make electrical contact with the interconnect system.
Reducing transistor die area and increasing transistor switching speed are important objectives in modern IC development. To minimize the risk of electrical failures such as short circuits, certain lateral alignment tolerance requirements must be followed during the fabrication of an IC. In satisfying these requirements, a sizable area normally must be allocated along the upper MS surface for the transistor semiconductive electrodes to contact the interconnect system. This restricts transistor scale-down efforts. More importantly, the parasitic capacitances that occur as a result of the substantial area needed for the contacts significantly limit the switching speed.
One promising technique for overcoming the contact area problem is to furnish the semiconductor die with a composite monosilicon/polysilicon layer More specifically, monosilicon is epitaxially deposited on certain sections of the upper MS surface, while polysilicon is deposited on dielectric material overlying other sections of the upper MS surface. The deposition is usually performed according to a chemical vapor deposition ("CVD") technique. By suitably doping the composite MS/PS layer with semiconductor impurities, transistor semiconductive electrodes and PN junctions are formed in the MS portions of the composite layer The PS portions of the layer provide intermediate electrical connections between these electrodes and an electrical interconnection system formed on the layer.
For a given fabrication capability, the contacts to the semiconductive electrodes formed in the composite MS/PS layer depend much less on the lateral alignment tolerance requirements than in the more conventional IC described earlier. Use of the MS/PS layer thereby allows transistor die area to be reduced. Since a concurrent decrease occurs in the associated parasitic capacitances, a substantial increase in transistor switching speed is also possible.
Mieno et al, "Novel Selective Poly- and Epitaxial-Silicon Growth (SPEG) Technique for ULSI Processing", Tech. Dio., 1987 Int'l Elec. Devs. Mtg., 1987, pp. 16-19, describe one technique used for creating a structure having such a composite MS/PS layer. The starting point in Mieno et al was a body consisting of a monosilicon substrate and an overlying field dielectric region formed with silicon dioxide Parts of the substrate were exposed through openings in the oxide.
Using disilane (Si.sub.2 H.sub.6) as a CVD silicon source, monosilicon was epitaxially grown on the exposed monosilicon of the body, while polysilicon was simultaneously deposited on the oxide. Hydrogen (H.sub.2) served as carrier gas for the disilane. The Si deposition was apparently performed in a single step in a suitable CVD chamber. The temperature T.sub.B of the body was 830.degree. C. during the CVD. The pressure P.sub.c of the chamber was 8000 pascal --i.e., about 60 torr. By suitably doping one such composite MS/PS layer, Mieno et al formed the base and emitter of an NPN bipolar transistor in the MS part of the layer. Mieno et al similarly formed the source and drain of an N-channel insulated-gate field-effect transistor in the MS part of another such MS/PS layer.
Thermal budget--i.e., basically the integral of time over the temperature that an IC experiences during its fabrication--is an important consideration in assessing the usefulness of a semiconductor fabrication technique such as that of Mieno et al. To achieve the shallow PN junctions (minimum dopant diffusions) needed for dense high-speed future ICs, the thermal budget generally needs to be low. If the thermal budget is too high, some of the PN junctions are driven too deep into the IC. The device performance is degraded, sometimes drastically.
The 830.degree. C. T.sub.B during the Si deposition in Mieno et al is relatively low. Consequently, Mieno et al appear capable of attaining a low thermal budget. Their fabrication process might, at first glance, seem well suited for making high-performance ICs.
Unfortunately, the disilane used by Mieno et al as a Si source is quite explosive, especially with halides. Disilane can ignite spontaneously. It is not a desirable gas for a semiconductor fabrication area if safer gases are available. Disilane is also quite expensive. Its price is approximately ten times that of silane (SiH.sub.4), another conventional CVD Si source.
Another reference of interest as background art to the present invention is Celler et al, U.S. Pat. No. 4,497,683. In Celler et al, a two-step silicon CVD is utilized to form a composite MS/PS layer on a body consisting of a monosilicon substrate and an adjoining silicon dioxide layer having openings through which the monosilicon is exposed. The first deposition step is a selective CVD in which monosilicon is epitaxially grown on the monosilicon at the bottom of the openings in order to fill them. Substantially no silicon accumulates on the oxide layer. The second deposition step entails epitaxially depositing monosilicon on the monosilicon that fills the openings and simultaneously depositing polysilicon on the oxide. Instead of directly using the resultant MS/PS layer to form a transistor, Celler et al laser recrystallize the layer in an effort to convert the polysilicon into monosilicon.
Celler et al specify that their CVD Si source may consist of silane, dichlorosilane (SiH.sub.2 Cl.sub.2), trichlorosilane (SiHCl.sub.3), or tetrachlorosilane (SiCl.sub.4) using hydrogen as carrier gas. The CVD is performed at atmospheric pressure and at a T.sub.B of 1050.degree. C. to 1250.degree. C. In the principal example disclosed in Celler et al, the body was heated in hydrogen after which the first CVD step was performed at 1150.degree. C. with tetrachlorosilane. The second CVD step was then done at 1050.degree. C. with silane. Although not described in the principal example, Celler et al elsewhere state that an etchant such as hydrochloric acid (HCl) is utilized during the first CVD step in order to make it selective.
Use of silane is advantageous because it is a conventional semiconductor fabrication gas. Its price is relatively low. Tetrachlorosilane is somewhat more expensive than silane but is an acceptable gas for a semiconductor fabrication area. However, the silicon CVD T.sub.B of 1050.degree. C. or more in Celler et al is quite high. Their thermal budget is high It would be quite difficult to use the process of Celler et al in manufacturing dense highspeed future ICs.
In summary, Mieno et al achieve a low thermal budget but use an undesirable Si source. Essentially the opposite occurs in Celler et al. They employ acceptable Si sources but have an undesirably high thermal budget. A process for depositing a composite MS/PS layer on a monosilicon/dielectric body at a low thermal budget using Si sources readily amenable to semiconductor fabrication would be quite desirable.